1. Field of the Invention
The present invention relates to data communications systems and methods, and more particularly, to bus bridge systems and methods.
2. Statement of the Problem
High bandwidth busses are typically used to communicate between hosts and peripherals in applications such as computer networks. The bus interfaces used by hosts and peripherals often take different forms depending on the performance characteristics desired. For example, host devices may communicate via a differential or single ended Small Computer System Interface (SCSI) or a Fibre Channel (FC) interface, while a peripheral such as a disk array may utilize a SCSI or other bus interface. When hosts and peripherals use disparate bus architectures, bus bridges are often utilized to provide connectivity.
Bus bridges may also be used to increase the capacity of bus systems. Bus specifications often limit, among other things, the length of the bus and the number of devices that may be attached to the bus in order to maintain performance. For example, the Peripheral Component Interconnect (PCI) bus specification commonly employed in personal computer bus applications has detailed rules for round trip propagation delay and capacitive loading which help maintain the integrity of communications at specified bus clock rates. In order to increase the capacity of such a bus, an expanded multi-layer bus structure may be used that includes a plurality of busses connected by high-speed bus bridges. This multi-layer structure can allow an increased number of devices to be interconnected while maintaining bus performance.
Complex computer systems and networks may employ multiple hosts connected to peripherals such as mass storage devices. These devices often are connected to the hosts by multiple busses and bus bridges. Consequently, data stored on these mass storage systems may be temporarily inaccessible due to a bus bridge failure, an event that can incur significant down time costs. In addition, systems that utilize bridges with storage elements, such as caches used in for Redundant Array of Independent Disk (RAID) systems that implement data striping or mirroring across multiple disks or other storage media, may be subject to data loss or corruption if the coherence of the cache is lost due to a bridge failure. Accordingly, it is desirable to increase the reliability of bus bridges to help reduce the likelihood of information loss.
Conventional approaches to increasing the reliability of bus bridge systems include so-called "N+1" power supply redundancy. According to such a scheme, a power source for a data communications system includes a ganged plurality of power supplies, typically supplying a common bus. The common bus is fed by a number of supplies sufficient to supply the load presented by the bus bridges and other components of the system, assuming all components are operational, as well as by an additional power supply, i.e., an "N+1st" power supply. Should one power supply fail, sufficient capacity should remain to keep the system operational. According to the theory of operation of such systems, the likelihood of multiple power supplies failing is relatively low, and therefore the additional N+1st supply provides sufficient redundancy.
Unfortunately, however, an N+1 system can have undesirable characteristics and may not be suitable for all applications. N+1 systems typically tie a plurality of power supplies to a common bus, and thus can present current sharing problems as well as vulnerability to failure of the common bus. In addition, some RAID controller systems are sold as discrete units that include one or more bus bridges and associated power supplies, and are not designed to supply power to other peripheral devices such as disk arrays. Providing N+1 redundancy in such systems can be wasteful. Accordingly, there is a need for alternative techniques for increasing reliability in redundant bus bridge systems.